In a semiconductor memory device in which a nonvolatile memory such as a NAND-type flash memory is used, addressing architecture that is specific to the memory device is controlled because such specific addressing architecture is required for wear leveling or the like. When there is a write request to a certain logical address from outside, the requested logical address is translated into a physical address indicating an actual recording position according to the addressing architecture inside the memory device. The write target data is recorded in the recording position in the flash memory indicated by the physical address.
Typically, the addressing architecture is controlled by using a table. The table for controlling the addressing architecture will be hereinafter referred to as an address translation table. The address translation table is stored in a volatile memory such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) provided in the semiconductor memory device, for example.
In recent years, however, errors such as soft errors occur in a SRAM, a DRAM or the like more and more frequently with miniaturization of semiconductor manufacturing processes. As a result, an error may occur in the address translation table itself. The embodiments therefore disclose a semiconductor memory device capable of correcting an error in an address translation table itself.